1. Microfiche Appendix
Not applicable.
2. Technical Field
The present invention relates to optical communication networks, and in particular to perforating pointer processing and path BIP-8 computation for large concatenated payloads within processing nodes of such a network.
Processing network nodes in current optical networks employing CMOS technology have to operate the limited speeds of this technology, which are well below currently available speeds of transmitting data over fiber optic links in such network. In addition, at a network processing node, data may be coming from several different sources, on different connections and at different line clocks. However, at the node, all data must be processed at a local system clock. Accordingly, pointer processor systems are used within processing network nodes to perform timing adjustments on incoming data, in converting the incoming data from a line clock domain to a local system clock domain or xe2x80x98shelf-timexe2x80x99 domain.
In order to be able to handle large data frames, pointer processors usually comprise several integrated circuits. In turn, each integrated circuit may comprise a plurality of processing strips, each processing strip having a limited data processing capacity.
A known pointer processor design for SONET (Synchronous Optical Network) or SDH (Synchronous Digital Hierarchy) type data frames is structured on STS (Synchronous Transmission Signal)-n level pointer processing strips, which are capable of processing the equivalent of n STS-1 building blocks from a SONET/SDH frame.
It is often desirable to be able to carry frames comprising large payloads, such as concatenated STS-Nc frames across pointer processing nodes. This implies that for N greater than n, concatenated payloads must be carried across several STS-n level pointer processing strips and possibly even across several chips, when the number of STS-n level pointer processing strips on a single chips is insufficient for the STS-Nc with N very large.
A SONET/SDH STS-Nc concatenated frame is built from N STS-1 building blocks pasted together, but information about the beginning of the SPE is kept only in the pointer bytes, H1 and H2, of the leading STS-1 block in the concatenation. In other words, only the leading STS-1 block in a concatenation comprises valid pointer information within its H1 and H2 bytes, whereas the H1 and H2 bytes of the trailing STS-1 blocks of the concatenation contain only a concatenation indication. On the other hand, in processing SONET/SDH frame on a pointer processing strip, the strip must have valid pointer information for all the STS-1 blocks within the processed frame. It follows that in processing a concatenated payload across several pointer processing strips, strips processing trailing STS-1 blocks in the concatenation must obtain the valid pointer information from the strip processing the leading STS-1 block in the concatenation.
FIG. 1 illustrates a general scheme of passing pointer information through a pointer processing strip or SYNC block, such that it can operate properly on SONET/SDH type data frames. The pointer processing strip has a pointer interpreter side and a pointer generator side. The pointer interpreter side, working in the line clock domain, receives the incoming data frames on the xe2x80x98Data-inxe2x80x99 line, interprets their overhead and writes (W) the payload in an Elastic Store. The pointer generator side, working in the system or shelf clock domain, reads (R) the payload from the Elastic Store and forms new SONET/SDH or other type frames to be passed further to the processing node on the xe2x80x98Data-outxe2x80x99 line. The generation of frames by the pointer generator side is based on a SYNC 8K signal, which is an 8 kHz reference indicating the phase of the frame to be formed. The writing and reading of the payload to and from the elastic store, respectively, must be done based on corresponding valid pointer information. In addition, due to the format of the SONET and SDH type frames, valid pointer information on either side of the pointer processor must be available before the reading of the H3 overhead byte, on the pointer interpreter side, or the generation of the H3 byte on the pointer generator side. This is due to the fact that the H3 byte may, in some cases, be part of the actual payload. Let A and B be ports of inputting pointer information to the pointer interpreter and the pointer generator sides, respectively, from a previous pointer processing strip, for example. Also, let Axe2x80x2 and Bxe2x80x2 be corresponding ports of outputting pointer information. Considering the pointer processing of a certain frame, let t1 be a moment in time when the H3 byte is read from the incoming data and to be a subsequent moment in time when the H3 byte is added to the generated frame, according to the SYNC 8K signal. According to the above, it follows that for the pointer processing strip to function properly, valid pointer information must be available at A before t1 and at B before t2. Furthermore, if this condition is met and letting xcex94t be the propagation delay of pointer information through the pointer processing strip, valid pointer information will be outputted at Axe2x80x2 on or before t1+xcex94t, and at Bxe2x80x2 on or before t2+xcex94t.
FIG. 2 illustrates a known scheme of passing pointer information along a sequence of pointer processing strips or SYNC blocks #1, #2, #3, etc. Data comes in simultaneously at all blocks on their pointer interpreter sides, through xe2x80x98Data-inxe2x80x99 lines. Likewise, data is generated on the xe2x80x98Data-outxe2x80x99 lines based on the same SYNC 8K signal running to all three blocks. Assuming that SYNC block #1 receives valid pointer information through A and B at t1 and t2, respectively, then SYNC block #2 receives the valid pointer information from SYNC block #1, at t1+xcex94t and t2+xcex94t, respectively, SYNC block #3 receives the valid pointer information at t1+2xcex94t and t2+2xcex94t, respectively, and so on. In order for the SYNC blocks to operate properly, the incoming H3 bytes must be read as follows: on or after t1 on SYNC block #1, on or after t1+xcex94t on SYNC block #2, on or after t1+2xcex94t on SYNC block #3, and so on. Similar conditions apply for the outgoing H3 bytes in the generated frames. It follows that in this design, only a limited number of pointer processing strips can be used to perform pointer processing on a concatenated payload. Specifically, the number of strips that can be used is roughly equal to T/xcex94t, where T is the length of the critical time region during which the pointer information must be propagated. Specifically, this critical time region is defined by time period between the moment when all the necessary pointer information on the strip is available, such as after the H1/H2 bytes of the last STS-3 leader on the strip has been read, and the moment when all the pointer information must be available on the next strip, which is the moment of processing the H3 byte of the first STS-1 block processed on that strip. In the SONET standard T is approximately 100 nanoseconds(ns). xcex94t is dependent on the technology and is currently of the order of several ns, depending on the capacity of the SYNC blocks. For example, one of the technologies currently owned by the assignee of this application, features a 25 ns pointer information propagation delay between STS-48 level processing strips. This implies that a concatenated payload cannot be carried across more than 4 such strips, limiting the size of the concatenation frame to an STS-192c.
In addition to the need for conveying pointer information downward from one SYNC block to the next, along a string of SYNC blocks spanning a concatenated payload, information must also be conveyed in an upward fashion. For example, when the pointer state of an STS-1 block within the concatenation is xe2x80x98AISxe2x80x99 (alarm indication signal), instead of xe2x80x98Vxe2x80x99, for valid pointer or xe2x80x98Cxe2x80x99 for concatenation indicator, such information is transmitted to preceding STS-1 blocks. From the information that travels upward across slices as indicated by the arrows U, especially important are frame error check values such as the B3 byte data, of which computation is commonly performed within the pointer processors. In the SONET standard, B3 is an path Bit Interleaved Parity-8 (BIP-8) byte. The value of a B3 byte in a given frame is calculated by XOR-ing the SPE bytes of the given frame starting with the J1 byte. The calculated B3 value for the given frame, must be checked against a transmitted B3 value for the given frame, which is located within the frame following the given frame in the transmission.
For a concatenated frame, the B3 value for the entire frame is kept in the B3 byte position of the leading STS-1 block in the concatenation and it is also calculated through an XOR operation over all SPE bytes in the frame. This calculation can be accomplished by XOR-ing the B3 values of all the STS-1 blocks in the concatenation. Accordingly, when a concatenation is split across several pointer processing strips, the B3 byte data must be sent upwards from strip to strip, until the strip containing the leading STS-1 block of the concatenation is reached.
It is an object of the invention to provide a novel pointer processing system and method for carrying large concatenated payloads across a processing node of an optical communications networks.
It is another object of the invention to provide a novel system and method for BIP-8 computation for large concatenated payloads within a processing node of an optical communication network.
According to one aspect of the invention, there is provided a pointer processor system comprising: an input port for receiving input data, a parallel array of pointer processing strips, for adjusting line clock domain input data to system clock domain output data, means for distributing input data from the input port to the pointer processing strips according to a distribution order, a pointer interpreter delay block controlling input data reading on at least a pair of an ith and jth pointer processing strips, such that corresponding input data is read on the jth pointer processing strip after a predetermined pointer interpreter pair delay from a time moment when corresponding input data is read on the ith pointer processing strip, wherein i and j are integers assigned to the pointer processing strips according to the distribution order and j is greater than i, means for collecting output data from the pointer-processing strips according to a collection order, and an output port for transmitting output data.
According to another aspect of the invention, in a digital optical network, a method of performing pointer processing on a concatenated payload is provided. The method comprises the steps of distributing the concatenated payload into a plurality of data slices according to a distribution order and performing pointer processing operations on at least a pair of an ith and jth data slices. The pointer processing step is performed such that pointer processing of a fixed byte within the jth data slice is performed after a predetermined pair delay from the pointer processing of a corresponding fixed point in the ith data slice, wherein i and j are integers assigned to the pointer processing strips according to the distribution order and j is greater than i.
According to a further aspect of the invention, there is provided a Bit Interleaved Parity-8 (BIP-8) computation system. The BIP-8 computation system frame processor, for computing new first frame BIP-8 values, storage means receiving second frame data from the frame processor for storing old first frame BIP-8 values, wherein the old first frame BIP-8 value is transmitted within the second frame, a comparator circuit receiving data from the BIP-8 computation block, from the storage means and from a critical time signalling circuit, for comparing the new first frame BIP-8 values with the old first frame BIP-8 values. The critical time signalling circuit sends an enabling signal to the comparator, for enabling the comparison operation according to a predetermined comparison timing schedule.
According to yet a further aspect of the invention there is provided a method of computing a local frame error check values for a data slice of a transmission frames processed at nodes of a digital optical network. The method comprises computing a calculated local frame error check value based on frame values received within a first transmission frame, storing a transmitted local frame error check values received within a second transmission frame; and comparing the calculated local frame error check value and the transmitted local frame error check value upon the reception of a comparison signal.
According to yet a further aspect of the invention, there is provided a pointer processing system for performing pointer processing on a large concatenated payload across multiple integrated circuits. The pointer processor system comprises a first integrated circuit, a second integrated circuit having a common chip boundary with the first integrated circuit, an array of pointer processing strips for performing pointer processing functions, each of which has a pointer interpreter for interpreting an input, a memory for storing the output of the pointer interpreter and a pointer generator for reading data from the memory and generating a frame, wherein the pointer processing strips are distributed on the first and second integrated circuits, a first inter-chip communication block located on the first integrated circuit near the common chip boundary and a second inter-chip communication block located on the second integrated circuit near the common chip boundary, for collecting information from pointer processing strips located on the first integrated circuit to pointer processing strips located on the second integrated circuit across the common chip boundary.
According to yet a further aspect of the invention there is provided a method of performing pointer processing on a concatenated payload across multiple integrated circuits, within a digital optical network. The method comprises distributing the concatenated payload into a string of data slices according to a distribution order, determining an across-chip pair of data slices within said string, wherein the across-chip pair comprises data slices requiring pointer processing on separate integrated circuits and transmitting pointer information from a first data slice in the across-chip pair to a second data slice in the across-chip pair. The transmission of the pointer information includes dividing the pointer information into a non-critical set and a critical set, transmitting the non-critical set of pointer information away from a critical region, serially and transmitting the critical set of pointer information within the critical region, asynchronously.
Among the advantages presented by the pointer processing method and system of the preferred embodiments of the invention is the ability to perform pointer processing and BIP-8 computation on very large concatenated payloads. Other advantages, objects, and features of the present invention will be readily apparent to those skilled in the art from a review of the following detailed description of preferred embodiments in conjunction with the accompanying drawings and claims.